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Giant piezoresistance at surfaces and interfaces

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Piezoresistance is defined as a change in electrical resistance with an applied mechanical stress. In the case of metals, the piezoresistance is related to a change in the physical dimensions of the conductor. In semiconductors, especially indirect gap semiconductors like silicon, an applied mechanical stress induces a change in the band structure of the material. In this case the piezoresistance is due mainly to a change in the mobility of the charge carriers. This effect, first measured at Bell Labs in the 1950s, is much larger than the piezoresistance due to geometric changes such as is observed in metals.

More exotic (quantum) forms of piezoresistance exist, particularly in semiconductor heterostructures at low temperatures. These effects too can be very large and may even exceed the piezoresistance of bulk semiconductors such as silicon. We study other unusual forms of piezoresistance.

      
Metal semiconductor hybrid structures fabricated at IEMN by Steve Arscott. Here the metal (light blue) is aluminium, and the semiconductor (dark blue) is p-type silicon. The white scale bars are 20 microns long.

You can also read about the work on metal semiconductor hybrid structures in the Physics News Update from the American Institute of Physics.

  

The piezo-pinch effect: the carrier density plotted on a log scale for a silicon nanowire at three different applied stresses. Hot (cold) colours correspond to a high (low) density.

A top-down fabricated, suspended silicon microwire whose piezoresistance is the same as that of bulk silicon.

You can also read about the work on silicon nano-structures in the PhysicsWorld interview Questions raised about giant piezoresistance, in the Physics Synopsis from the American Physical Society or in this Nature Materials research highlight.

One example is the so called “extraordinary piezoconductance” or EPC measured in hybrid metal/semiconductor structures (see figure to the right). By carefully choosing the form of the hybrid structure it is possible to use the bulk piezoresistance of a silicon part to switch on or off the metallic (short circuit) part of the hybrid. Since there is a large difference in the electrical conductivity of the metal and the semiconductor, this can lead to large piezoresistive effects, almost one order of magnitude bigger than that measured in bulk silicon.

"Giant room-temperature piezoresistance in a metal-silicon hybrid structure", A.C.H. Rowe, A. Donoso-Barrera, Ch. Renner and S. Arscott, Phys. Rev. Lett. 100, 145501 (2008)

A second example is the giant piezoresistance first reported by He and Yang in bottom-up silicon nanowires. A simple model to explain this phenomenon - the piezopinch effect - was first described by us and relates a change in the width of the surface depletion layer due to the applied mechanical stress. We recently tried to experimentally verify this interpretation by investigating the piezoresistive properties of a range of top-down silicon nano- and micro-structures. By carefully separating surface charging effects from the true piezoresistive, we controversially find that the piezoresistance is comparable to that of bulk silicon. The debate now turns on whether the surfaces of top-down and bottom-up wires are fundamentally different from an electrostatic viewpoint.

"Silicon nanowires feel the pinch", A.C.H. Rowe, Nature Nanotechnology 3, 311 (2008)

"Giant Piezoresistance Effects in Silicon Nanowires and Microwires", J.S. Milne, A.C.H. Rowe, S. Arscott and Ch. Renner, Phys. Rev. Lett. 105, 226802 (2010)